1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming alignment marks and overlay marks on integrated circuit products that employ FinFET semiconductor devices, and the associated products that include such alignment marks.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as so-called short channel effects, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a generally planar structure, there are so-called 3D devices, such as a FinFET device, which has a three-dimensional structure. More specifically, in a FinFET, one or more generally vertically positioned, fin-shaped active areas are formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active areas to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width under the channel and thereby reduce the short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
In general, manufacturing semiconductor devices involves performing numerous process operations, e.g., deposition processes, etching processes, ion implanting processes, lithography processes, heating processes, etc., in a given sequence or process flow to form the desired integrated circuit product. The device is manufactured, more or less, layer-by-layer until the device is completed. In manufacturing integrated circuit devices, it is vitally important that a subsequently formed structure or layer be accurately located or positioned relative to a previously formed layer or structure. Without proper alignment of the structures and layers as the device is formed, the device may not operate as efficiently as intended or, in some cases, may not operate at all. For example, if a conductive contact to a gate structure of a transistor is misaligned to the point that it does not conductively contact the intended gate structure, then the transistor will not function. As another example, even in cases where a first and second conductive contact are sufficiently aligned such that there is a conductive path established between the two structures, there may be sufficient misalignment between the conductive contacts such that the resistance between the two conductive contacts is greater than anticipated by the design process, thereby leading to reduced operating efficiencies. In an effort to insure proper alignment of the various structures and layers during semiconductor device manufacturing, manufacturers employ various alignment marks and overlay techniques. Such alignment marks may take a variety of forms, e.g., cross-shaped, chevron-type patterns, a grid of lines, numbers, letters, etc. The number and location of such alignment marks may vary depending on the particular application and/or the device under construction. For example, such alignment marks may be located in the scribe lines of a substrate.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. In general, the fins of a FinFET semiconductor device are formed by etching a plurality of fin-forming trenches in a semiconducting substrate. As FinFET devices have been scaled to meet ever increasing performance and size requirements, the width of the fins has become very small, and the fin pitch has also been significantly decreased. One manufacturing technique that is employed in manufacturing FinFET devices employing such small fins and having such small fin pitches is to initially form a so-called “sea-of-fins” across the substrate. Thereafter, some of the fins are removed from areas where isolation regions will be formed. Using this “sea-of-fins” type manufacturing approach, better accuracy and repeatability may be achieved in forming the fins to very small dimensions due to the more uniform environment in which the etching process that forms the fin-forming trenches, and thus the fins, is performed.
FIGS. 1A-1B are a cross-sectional view and a plan view, respectively, of a discrete portion of an illustrative integrated circuit product 10 at an early stage of manufacture. The product 10 is at the point of fabrication where the “sea-of-fins” 16 has been initially formed by forming a plurality of fin-forming trenches 20 in the substrate 12. In one example, the width 16W of the fins 16 may be about 10-20 nm, and the fin pitch 16P may be on the order of about 30-80 nm. The depth 20D of the fin-forming trenches 20 may be on the order of about 70-200 nm. A layer of insulating material 22, e.g., silicon dioxide, is positioned between the fins 16 at this point in the process. The structure depicted in FIGS. 1A, 1B may be achieved by etching the substrate 12 through a patterned mask layer, typically a hard mask layer, to define the fin-forming trenches 20, over-filling the trenches 20 with the insulating material 22 and performing one or more chemical mechanical polishing (CMP) processes to remove the excess insulating material 22 positioned outside of the fin-forming trenches 20. The hard mask layer may be formed by performing traditional deposition/photolithography/etching techniques. In other cases, the hard mask layer may be formed by performing well-known sidewall image transfer techniques.
FIGS. 1C-1D are a cross-sectional view and a plan view, respectively, of the product 10 at a very high level so as to show, in a relative sense, the formation of physically larger structures on the substrate 12. In FIGS. 1C-1D, the fins 16 are depicted as isolated dark lines with insulating material 22, such as silicon dioxide, positioned between the fins 16. FIG. 1C just depicts the “sea of fins” 16, whereas FIG. 1D depicts a portion of the product 10 that includes a relatively large region 22A of insulating material where an illustrative, cross-shaped alignment mark 24 has been formed. In general, the alignment mark 24 is formed from a subset or portion of the plurality of the individual fins 16 and it is surrounded by the large region 22A of insulating material. While the individual fins 16 are very small, the alignment mark 24 is, in a relative sense, much larger. For example, the alignment mark 24 may have an overall height 24H that may be about 2-4 μm and an overall width 24W of about 2-4 μm. The dimension 24X may be on the order of about 1 μm.
The alignment mark 24 may be formed as follows. After the “sea-of-fins” 16 has been formed, as shown in FIG. 1C, some of the fins 16 (or portions thereof) must be removed to create room for the isolation structures (not shown) that will ultimately be formed to electrically isolate the individual FinFET devices, and the area to be occupied by the large region 22A of insulating material where the alignment mark 24 will be formed after the large region 22A is filled with insulating material 22. FIG. 1D, depicts the device 10 after the insulating material 22 has been deposited on the substrate and after a CMP process has been performed that typically stops on the fins 16. This process effectively defines the alignment mark 24 that is positioned in the large area 22A of insulating material and fills the fin-forming trenches 20 in the remaining portions of the sea-of-fins 16. The tools and equipment that use the alignment mark 24 for alignment purposes can detect or “see” a difference between the silicon fins 16 and the surrounding large area 22A of insulating material 22 and thereby recognize and align to the alignment mark 24.
While the aforementioned process has been used to form integrated circuit products that employ FinFET devices, it is not without drawbacks. More specifically, the CMP processes that are performed to planarize the upper surface 22S (see FIG. 1A) of the layer of insulating material 22 with the upper surface 16S (see FIG. 1A) of the fins 16 are very difficult to control. Moreover, trying to form the alignment mark 24 from a relatively isolated group of the relatively small fins 16 within the relatively large area 22A of insulating material 22 may lead to certain problems. For example, as shown in FIG. 1E, such CMP processes may lead to unacceptable dishing or smearing of the isolation material 22 and or destruction of at least the upper portion of some of the fins 16, as indicated with the reference number 25. As a result, the alignment mark 24 becomes distorted from what is intended by the design process. Such distortion of the alignment mark 24 can make it more difficult if not impossible to locate and/or to make proper alignments relative to the now-distorted alignment mark 24 depicted in FIG. 1E.
The present disclosure is directed to various methods of forming alignment marks on integrated circuit products that employ FinFET devices, and integrated circuit products incorporating such alignment marks, that may solve or reduce one or more of the problems identified above.